1. Field of the Invention
The present invention relates to a delay circuit equipped with a clock circuit and a counter circuit for producing desirable delay time by using a clock signal outputted from the clock circuit.
2. Description of the Related Art
Referring now to FIG. 7, an example of a conventional delay circuit will be described.
In this conventional delay circuit, an input signal of a delay circuit 101 constitutes an input signal for a clock circuit 102. This clock circuit 102 outputs a rectangular wave signal having a constant time period as an output signal after such a time instant when the above-described input signal is entered to this clock circuit 102. An input signal of a counter circuit 103 corresponds to the output signal of the clock circuit 102. While the counter circuit 103 senses such a condition that a signal level of an input signal is changed from either a high level to a low level or a low level to a high level, the counter circuit 103 outputs such an output signal having a high level when a total wave number of the rectangular waves corresponding to the input signal thereof becomes a predetermined number.
An AND gate circuit 107 senses such a state that both the input signal level of the delay circuit 101 and the output signal level of the counter circuit 103 become high levels, so that this AND gate circuit 107 outputs an output signal of the delay circuit 101.
As a result, as shown in FIG. 8, delay time of this delay circuit 101 is equal to:
detected wave number of counter circuit 103xc3x97time period of signal outputted from clock circuit 102xe2x80x83xe2x80x83(1).
In the above-described conventional delay circuit 101, a measuring terminal 201 is provided between the output terminal of the clock circuit 102 and the input terminal of the counter circuit 103 so as to test delay time of this delay circuit 101. This delay time test may be carried out as follows. That is, a time period of an output signal of the clock circuit 102 may be measured by using this measuring terminal 201. Also, while such a rectangular wave having a shorter time period than the time period of the output signal of the clock circuit 102 is inputted so as to shorten the delay time of the delay circuit 101, the shortened delay time may be tested. However, in the case that the delay circuit 101 is made by employing the above-described circuit arrangement, there is the below-mentioned problem.
In the case that this delay circuit 101 is used, when the measuring terminal 201 is short-circuited to either the power supply voltage (will be referred to as a xe2x80x9cVDDxe2x80x9d hereinafter) or the ground potential (will be referred to as a xe2x80x9cVSSxe2x80x9d hereinafter), the signal level of the input signal of the counter circuit 103 is not changed from either the high level to the low level or from the low level to the high level. As a result, the counter circuit 103 cannot produce the output signal, but also the delay circuit 101 cannot be operated under normal condition, so that this delay circuit 101 cannot produce the output signal.
In general, circuits provided for protection purposes and also provided in order to improve safety characteristics should be continuously brought into a so-called xe2x80x9cfail safexe2x80x9d state. Namely, even when a failure happens to occur in these circuits, certain sorts of protection may be made. In the case of delay circuits, even when delay time thereof is not equal to defined delay time values, these delay circuits are necessarily required to be operated in such a manner that output voltages thereof are inverted, and thus, signals are sent out from these delay circuits.
The present invention has been made to solve the above-explained problem, and therefore, has an object to provide such a delay circuit comprising: a clock circuit for outputting at least a clock having a constant time period; a measuring terminal capable of measuring the clock output of said clock circuit; and a counter circuit for producing desirable delay time by using the clock output of the clock circuit; in which; even when the measuring terminal capable of measuring the clock output of the clock circuit is short-circuited to another wiring line, the delay circuit firmly controls charge and discharge operations.
In other words, a voltage detecting circuit is additionally employed in the delay circuit. This voltage detecting circuit detects such a condition that a voltage appeared at a measuring terminal of the delay circuit is shifted from a predetermined voltage range for a time duration longer than, or equal to a preset time duration. Even when the measuring terminal of the delay circuit is short-circuited to the power supply voltage, or the ground potential, this delay circuit can firmly invert the output signal level based on delay time set by an internal delay circuit.